In recent years, flash memories such as floating gate flash memories have been widely used in electronic products such as digital cameras, camcorders, mobile phones, mobile computers, etc. Advantages of flash memories include non-volatility, i.e., information may be stored in the memory even when power supply is disconnected, and fast erasure speed. A floating gate flash memory may be manufactured on a semiconductor substrate and generally includes an array of memory cells each having a control gate and a floating gates. Electric charges may be stored in the floating gate, thereby changing a status of the respective memory cell. The structure of a conventional floating gate flash memory 100 is described in the following with reference to FIG. 1.
FIG. 1 shows a cross-sectional view of a part of floating gate memory 100 formed on a semiconductor substrate 102. A memory cell 104 of memory 100 as shown in FIG. 1 includes a source region 106 and a drain region 108 formed in substrate 102, a floating gate 110, and a control gate 112. A first layer of oxide 114 is formed between floating gate 110 and substrate 102. A protection layer 116 is formed above floating gate 110. A second layer of oxide 118 isolates control gate 112 from floating gate 110. A source line 120 is formed to provide contact to source region 106. An interlayer dielectric (ILD) 122 is formed above control gate 112, protection layer 116, and source line 120. ILD 122 has formed therein a via hole 124. A bit line contact 126 is formed to provide contact to drain region 108. A first spacer 128 is formed on sidewalls of floating gate 110 and protection layer 116 and isolates source line 120 from floating gate 110. A second spacer 130 is formed on a sidewall of control gate 112.
Problems associated with memory cell 104 as shown in FIG. 1 are that a thickness and a critical dimension (CD) of control gate 112 are hard to control during fabrication and that, because control gate 112 must be spaced apart from bit line contact 126 by a distance (indicated by “L” in FIG. 1) to avoid short circuit, a degree of integration is limited. Further, during the fabrication of memory 100, misalignments of masks used in photolithography steps may result in open circuits or short circuits, thus affecting yield of fabrication.